www.lansdale.com page 1 of 10 issue a ml145406 driver/receiver eia 232 e and ccitt v.28 (formerly rs 232 d) legacy device: motorola mc145406 the ml145406 is a silicon gate cmos ic that combines three drivers and three receivers to fulfill the electrical specifications of standards eia 232 e and ccitt v.28. the drivers feature true ttl input compatibility, slew rate limited output, 300 power off source impedance, and output typ- ically switching to within 25% of the supply rails. the receivers can handle up to 25 v while presenting 3 to 7 k impedance. hysteresis in the receivers aids reception of noisy signals. by combining both drivers and receivers in a single cmos chip, the ml145406 provides efficient, low power solutions for eia 232 e and v.28 applications. this device offers the following performance features: operating temperature range = t a 40 to +85 c drivers 5 v to 12 v supply range 300 power off source impedance output current limiting ttl compatible maximum slew rate = 30 v/ s receivers 25 v input voltage range when v dd = 12 v, v ss = 12 v 3 to 7 k input impedance hysteresis on input switchpoint p dip 16 = ep plastic case 648 so 16w = -5p sog case 751g 16 1 16 1 cross reference/ordering information motorola p dip 16 mc145406p ml145406ep so 16w MC145406DW ml145406-6p lansdale package note : lansdale lead free ( pb ) product, as it becomes available, will be identified by a part number prefix change from ml to mle . pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 r d v dd rx1 tx1 rx2 tx2 rx3 tx3 v ss v cc do1 di1 do2 di2 do3 di3 gnd d = driver r = receiver r r d d block diagram v dd receiver v cc do di 1.4 v hysteresis 1.8 v 1.0 v driver level shift 300 tx v ss 5.4 k rx 15 k *protection circuit v cc v dd v dd v cc v ss + + *
www.lansdale.com page 2 of 10 issue a lansdale semiconductor, inc. ml145406 maximum ratings (voltage polarities referenced to gnd) rating symbol value unit dc supply voltages (v dd v cc ) v dd v ss v cc ?0.5 to + 13.5 + 0.5 to ?13.5 ?0.5 to + 6.0 v input voltage range rx1? inputs di1? inputs v ir (v ss ?15) to (v dd + 15) ?0.5 to (v cc + 0.5) v dc current per pin 100 ma power dissipation p d 1.0 w operating temperature range t a ?40 to + 85 c storage temperature rate t stg ?85 to + 150 c dc electrical characteristics (all polarities referenced to gnd = 0 v, t a = ?40 to + 85 c) parameter symbol min typ max unit dc supply voltage v dd v ss v cc (v dd v cc ) v dd v ss v cc 4.5 4.5 4.5 5 to 12 5 to ? 12 5.0 13.2 13.2 5.5 v quiescent supply current (outputs unloaded, inputs low) v dd = + 12 v v ss = 12 v v cc = + 5 v i dd i ss i cc 140 340 300 400 600 450 a receiver electrical specifications (voltage polarities referenced to gnd = 0 v, v dd = + 5 to + 12 v, v ss = 5 to ? 12 v, v dd v cc , t a = 40 to + 85 c) characteristic symbol min typ max unit input turn?n threshold rx1?x3 v do1?o3 = v ol , v cc = 5.0 v 5% v on 1.35 1.80 2.35 v input turn?ff threshold rx1?x3 v do1?o3 = v oh , v cc = 5.0 v 5% v off 0.75 1.00 1.25 v input threshold hysteresis rx1?x3 v cc = 5.0 v 5% v on ? off 0.6 0.8 v input resistance rx1?x3 (v ss 15 v) v rx1?x3 (v dd + 15 v) r in 3.0 5.4 7.0 k high?evel output voltage (v rx1?x3 = ? 3 v to (v ss ?15 v))* do1?o3 i oh = ? 20 a, v cc = + 5.0 v i oh = 1 ma, v cc = + 5.0 v v oh 4.9 3.8 4.9 4.3 v low?evel output voltage (v rx1?x3 = + 3 v to (v dd + 15 v))* do1?o3 i ol = + 20 a, v cc = + 5.0 v i ol = + 2 ma, v cc = + 5.0 v i ol = + 4 ma, v cc = + 5.0 v v ol 0.01 0.02 0.5 0.1 0.5 0.7 v * this is the range of input voltages as specified by eia 232? to cause a receiver to be in the high or low logic state. this device contains protection circuitry to pro- tect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applica- tion of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation, it is recommended that the voltages at the di and do pins be constrained to the range gnd v di v cc and gnd v do v cc . also, the voltage at the rx pin should be constrained to (v ss ?15 v) v rx1? (v dd + 15 v), and tx should be constrained to v ss v tx1? v dd . unused inputs must always be tied to an ap- propriate logic voltage level (e.g., gnd or v cc for di and ground for rx.)
www.lansdale.com page 3 of 10 issue a lansdale semiconductor, inc. ml145406 electrical specifications (voltage polarities referenced to gnd = 0 v, v cc = + 5 v 5%, t a = ?40 to + 85 c) characteristic symbol min typ max unit digital input voltage di1?i3 logic 0 logic 1 v il v ih 2.0 0.8 v input current di1?i3 v di1?i3 = v cc i in 1.0 a output high voltage (v di1? = logic 0, r l = 3.0 k ) tx1?x3 v dd = + 5.0 v, v ss = 5.0 v v dd = + 6.0 v, v ss = ? 6.0 v dd = + 12.0 v, v ss = 12.0 v v oh 3.5 4.3 9.2 3.9 4.7 9.5 v output low voltage* (v di1? = logic 1, r l = 3.0 k ) tx1?x3 v dd = + 5.0 v, v ss = ? 5.0 v v dd = + 6.0 v, v ss = ? 6.0 v v dd = + 12.0 v, v ss = ? 12.0 v v ol ? 4.0 4.5 10.0 4.3 5.2 ? 10.3 v off source resistance (figure 1) tx1?x3 v dd = v ss = gnd = 0 v, v tx1?x3 = 2.0 v 300 output short?ircuit current (v dd = + 12.0 v, v ss = ? 12.0 v) tx1?x3 tx1?x3 shorted to gnd** tx1?x3 shorted to 15.0 v*** i sc 22 60 60 100 ma * the voltage specifications are in terms of absolute values. ** specification is for one tx output pin to be shorted at a time. should all three driver outputs be shorted simultaneously, de vice power dissipation limits will be exceeded. *** this condition could exceed package limitations. switching characteristics (v cc = + 5 v 5%, t a = 40 to + 85 c drivers characteristic symbol min typ max unit propagation delay time tx1?x3 low?o?igh r l = 3 k , c l = 50 pf t plh 300 500 ns high?o?ow r l = 3 k c l = 50 pf t phl 300 500 output slew rate tx1?x3 minimum load r l = 7 k , c l = 0 pf, v dd = + 6 to + 12 v, v ss = 6 to 12 v sr 9 30 v/ s maximum load r l = 3 k , c l = 2500 pf v dd = + 12 v, v ss = ? 12 v v dd = + 5 v, v ss = ? 5 v 4 receivers (c l = 50 pf) characteristic symbol min typ max unit propagation delay time do1?o3 low?o?igh t plh 150 425 ns high?o?ow t phl 150 425 output rise time do1?o3 t r 250 400 ns output fall time do1?o3 t f 40 100 ns
www.lansdale.com page 4 of 10 issue a lansdale semiconductor, inc. ml145406 v in = 2v 3 5 7 14 12 10 89 1 16 v dd v cc di1 di2 di3 v ss gnd tx3 tx2 tx1 r out = v in i figure 1. power?ff source resistance (drivers) figure 2. switching characteristics figure 3. slew?ate characterization drivers di1?i3 3 v 0 v v oh v ol tx1?x3 t plh t phl 50% t f t r 10% 90% receivers rx1?x3 do1?o3 + 3 v 0 v v oh v ol t plh t phl t f t r 50% drivers tx1?x3 90% 50% 3 v ?3 v 3 v ?3 v t shl t slh slew rate (sr) = ?3 v ?(3 v) or 3 v ?( ?3 v) t slh t shl 10% p in d e scri p tions vdd p ositive p ower supply ( p in 1) the most positive power supply pin, which is typically + 5 to +12v. vss negative p ower supply ( p in 8) the most negative power supply pin, which is typically ?5 to ?2 v. v cc digital p ower supply ( p in 16) the digital supply pin, which is connected to the logic power sup- ply (maximum +5.5 v). v cc must be less than or equal to v dd . gnd ground ( p in 9) ground return pin is typically connected to the signal ground pin of the eia 232? connector (pin 7) as well as to the logic power supply ground. rx1, rx2, rx3 receive data input ( p ins 2, 4, 6) these are the eia 232? receive signal inputs whose volt- ages can range from (v dd + 15 v) to (v ss ?15 v). a volt- age between +3 and (v dd + 15 v) is decoded as a space and causes the corresponding do pin to swing to ground (0v); a voltage between ?3 and (vdd ?15 v) is decoded as a mark and causes the do pin to swing up to v cc . the actual turn?n input switch point is typically biased at 1.8 v above ground, and includes 800mv of hysteresis for noise rejection. the nominal input impedance is 5 k . an open or grounded input pin is interpreted as a mark, forcing the do pin to v cc . do1, do2, do3 data output ( p ins 11, 13, 15) these are the receiver digital output pins, which swing from v cc to gnd. a space on the rx pin causes do to produce a logic 0; a mark produces a logic 1. each output pin is capable of driving one lsttl input load. di1, di2, di3 data input ( p ins 10, 12,14) these are the high?mpedance digital input pins to the driv- ers. ttl compatibility is accomplished by biasing the input switchpoint at 1.4 v above gnd. however, 5v cmos compat- ibility is maintained as well. input voltage levels on these pins must be between v cc and gnd. tx1, tx2, tx3 transmit data output( p ins 3, 5, 7) these are the eia 232? transmit signal output pins, which swing toward v dd and v ss . a logic 1 at a di input causes the corresponding tx output to swing toward v ss . a logic 0 caus- es the output to swing toward v dd (the output voltages will be slightly less than v dd or v ss depending upon the output load). output slew rates are limited to a maximum of 30 v per ?. when the ml145406 is off (v dd = v ss = v cc = gnd), the minimum output impedance is 300 .
www.lansdale.com page 5 of 10 issue a lansdale semiconductor, inc. ml145406 the ml145406 has been designed to meet the electrical- specifications of standards eia 232? and ccitt v.28. eia 232? defines the electrical and physical interface between data communication equipment (dce) and dataterminal equipment (dte). a dce is connected to a dte using a cable that typically carries up to 25 leads. these leads, referred to as interchange circuits, allow the transfer of timing, data, control, and test signals. electrically this transfer requires level shifting between the ttl/cmos logic levels of the computer or modem and the high voltage levels of eia 232?, which can range from ? to ?5 v. the ml145406 provides the neces- sary level shifting as well as meeting other aspects of the eia 232? specification. driv e rs as defined by the specification, an eia 232? driver pres- ents a voltage of between ? to ?5 v into a load of between 3 to 7 k . a logic 1 at the driver input results in a voltage of between ? to ?15 v. a logic 0 results in a voltage between + 5 to + 15v. when operating v dd and v ss at ? to ?2 v, the ml145406 meets this requirement. when operating at ? v, the ml145406 drivers produce less than ? v at the output (when terminated), which does not meet eia 232? specifica- tion. however, the output voltages when using a ? v power supply are high enough (around ? v) to permit proper recep- tion by an eia 232? receiver, and can be used in applications where strict compliance to eia 232? is not required. another requirement of the ml145406 drivers is that they withstand a short to another driver in the eia 232? cable. the worst?ase condition that is permitted by eia 232? is a ?5v source that is current limited to 500 ma. the ml145406 drivers can withstand this condition momentarily. in most short circuit conditions the source driver will have a series 300 output impedance needed to satisfy the eia 232? driver requirements. this will reduce the short circuit current to under 40 ma which is an acceptable level for the ml145406 to withstand. unlike some other drivers, the ml145406 drivers feature an internally?imited output slew?ate that does not exceed 30 v per ?. r e c e iv e rs the job of an eia 232? receiver is to level?hift voltages in the range of ?25 to + 25 v down to ttl/cmos logic lev- els (0 to + 5 v). a voltage of between ?3 and ?25 v on rx1 is defined as a mark and produces a logic 1 at do1. a voltage between + 3 and + 25 v is a space and produces a logic zero. while receiving these signals, the rx inputs must present a resistance between 3 and 7 k . nominally, the input resistance of the rx1?x3 inputs is 5.4 k . the input threshold of the rx1?x3 inputs is typically biased at 1.8 v above ground (gnd) with typically 800 mv of hysteresis included to improve noise immunity. the 1.8 v bias forces the appropriate do pin to a logic 1 when its rx input is open or grounded as called for in the eia 232? specification. notice that ttl logic levels can be applied to the rx inputs in lieu of normal eia 232? signal levels. this might be helpful in situations where access to the modem or computer through the eia 232? connector is necessary with ttl devices. however, it is important not to connect the eia 232? outputs (tx1?x3) to ttl inputs since ttl operates off + 5 v only, and may be damaged by the high output voltage of the ml145406. the do outputs are to be connected to a ttl or cmos input (such as an input to a modem chip). these outputs will swing from v cc to ground, allowing the designer to operate the do and di pins from digital power supply. the tx and rx sections are independently powered by v dd andv ss so that one may run logic at + 5 v and the eia 232? signals at ?2v. p ow e r su pp ly consid e rations figure 4 shows a technique to guard against excessive device current. the diode d1 prevents excessive current from flowing through an internal diode from the v cc pin to the v dd pin when v dd < v cc by approximately 0.6 v. this high current condition can exist for a short period of time during powerup/down. additionally, if the + 12 v supply is switched off while the + 5 v is on and the off supply is a low impedance to ground, the diode d1 will prevent current flow through the internal diode. the diode d2 is used as a voltage clamp, to prevent v ss from drifting positive to v cc , in the event that power is removed from v ss (pin 12). if v ss power is removed, and the impedance from the v ss pin to ground is greater than approxi- mately 3 k , this pin will be pulled to v cc by internal circuit- ry causing excessive current in the v cc pin. if by design, neither of the above conditions are allowed to exist, then the diodes d1 and d2 are not required. e sd p rot e ction esd protection on ic devices that have their pins accessible to the outside world is essential. high static voltages applied to the pins when someone touches them either directly or indi- rectly can cause damage to gate oxides and transistor junctions by coupling a portion of the energy from the i/o pin to the power supply buses of the ic. this coupling will usually occur through the internal esd protection diodes. the key to protect- ing the ic is to shunt as much of the energy to ground as pos- sible before it enters the ic. figure 4 shows a technique which will clamp the esd voltage at approximately ?5 v using the mmvz15vdlt1. any residual voltage which appears on the supply pins is shunted to ground through the capacitors c1?3. this scheme has provided protection to the interface part up to ?0kv, using the human body model test. legacy applications information
www.lansdale.com page 6 of 10 issue a lansdale semiconductor, inc. ml145406 0.1 f v cc 0.1 f v dd ml145406 1 16 2 15 3 14 4 13 5 12 6 11 7 10 89 v ss 0.1 f rxi txo rxi txo rxi txo to connector mmbz15vdlt 6 in4001 in5818 d1 c1 c2 d2 c3 figure 4. esd and power supply networks legacy applications information
www.lansdale.com page 7 of 10 issue a lansdale semiconductor, inc. ml145406 17 20 k nc do3 10 f r tla** dtmf input r dsi 20 k c dsi 6 9 1 15 8 3.579 mhz 3 11 5 14 2 13 7 12 4 19 10 18 16 v dd tla dsi x in x out cd txd txa rxa2 rxa1 exi fb v ag cdt gnd cda lb sqt rxd r tx 600 + 10 k tip 600:600 ring v dd v dd bypass c fb mode + 5 v 1 ml145442/3 10 k 10 k c cda** 0.1 f c cdt v ss bypass 14 15 12 13 10 11 89 6 7 4 5 2 3 8 2 3 7 eia 232? db?5 connector nc nc v ss gnd di3 do2 di2 do1 di1 v dd v cc ml145406 tx1 rx1 tx2 rx2 tx3 rx3 1 6 ?5 v *line protection circuit **refer to the applications information for values of c cda and r tla 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 10 k 10 k * 0.1 f 0.1 f 0.1 f figure 5. 5? 300?aud modem with eia 232? interface
www.lansdale.com page 8 of 10 issue a lansdale semiconductor, inc. ml145406 1 2 3 4 5 6 7 8 9 0 * # twisted pair mc34119 speaker driver mc145412/13/16 pulse/tone dialer hookswitch ml145503 filter/ codec ringing mc145426 udlt line interface (transformer and protection) connection to external terminal or pc ml145406 rs?32 driver receiver ml145428 data set interface + 5 v gnd ?5 v mc34129 switching power supply (isolated) line filter sync figure 6. line?owered voice/data telephone with electrically isolated eia 232? interface legacy applications information
www.lansdale.com page 9 of 10 issue a lansdale semiconductor, inc. ml145406 c c v c c v c c v c c v d d v c c v c c v d d v d d v d d v d d v d d v s s v s s v s s v s s v s s v 1 n i f e r v 1 . 0 f 1 . 0 1 . 0 f f 0 . 1 * * f 1 . 0 f 1 . 0 f 5 r 6 r s d x t s t r d c s t c x r g s 2 4 8 5 3 7 4 1 c 5 2 - b d c c v 6 0 4 5 4 1 l m 1 x r 2 x r 3 x r 1 x t 2 x t 3 x t 1 o d 2 o d 3 o d 1 i d 2 i d 3 i d 1 8 2 4 6 3 5 7 9 6 1 5 1 3 1 1 1 2 1 0 1 4 1 c n c n c n c n c n c n 1 s 1 r d n g 2 d 1 q1 q q2 q 1 q 1 d 2 q 2 s 2 c 1 4 3 3 1 4 1 7 2 1 5 6 2 8 9 0 1 1 1 c n c n t s t s t s t s t s t s 4 7 c h 4 7 c m c b s x r d x t l d k l c r b d x r 1 r b 2 r b 3 r b b s s x t t e s e r o c d e o d c d e i d i c d m c 8 2 4 5 4 1 l m 5 2 1 0 2 6 1 3 1 4 1 5 1 7 1 8 1 9 1 1 2 3 4 1 1 6 7 8 9 0 1 1 . 0 f c n c n 4 t u o 2 t u o 4 n i 3 n i 3 t u o 1 t u o 5 n i 6 n i 6 t u o5 t u o 2 n i b u 9 6 0 4 1 c m 7 4 1 9 8 4 5 6 1 2 3 1 1 3 1 0 1 2 1 f p 0 2 f p 0 2 m 0 1 6 9 0 . 4 z h m z h m 8 4 0 . 2 z h k 8 2 1 z h m 8 0 0 0 1 * f p c n c n c n c n c n c n b q a 1 q c a a 2 q a 3 q b 1 q b 2 q b 3 q b 4 q a 4 q a r b 2 q d n g 3 9 3 c h 4 7 c m 5 4 3 1 4 1 2 7 2 1 1 1 0 1 9 8 3 1 6 c nt s t s z h m 6 9 0 . 4 1 2 0 2 8 1 9 1 7 1 4 1 2 1 5 1 4 5 8 9 6 1 1 1 3 1 1 2 2 2 0 1 3 6 7 x r 1 e r c d r / c d t 1 e t i s m x t 1 o l 2 o l 1 l 1 i s 1 o s e i s e s b l d v 2 i s 2 o s i c c d p 2 2 4 5 4 1 l m 1 d 2 d k 0 1 0 2 2 0 2 2 p i t g n i r tr1 c n c n 1 t 9 8 7 6 5 0 1 1 2 3 4 . g n i r e t l i f l a n o i t p o r o f * . d e s u s i r o t i c a p a c s i h t n e h w t u c e b d l u o h s 1 r t * * p a r t s t s n o i t c e n n o c o n c n v 5 = v 0 = d n g d n a c c v d d v n o i t c e s d - 2 3 2 - a i e e h t n i d e s s u c s i d e r a s s v d n g 1 c 2 r figure 7. 80?bps limited distance modem with eia 232? interface (master) legacy applications information
www.lansdale.com page 10 of 10 issue a lansdale semiconductor, inc. ml145406 outline dimensions p dip 16 = ep (ml145406ep) case 648?8 min min max max inches millimeters dim a b c d f g h j k l m s 18.80 6.35 3.69 0.39 1.02 0.21 2.80 7.50 0 0.51 19.55 6.85 4.44 0.53 1.77 0.38 3.30 7.74 10 1.01 0.740 0.250 0.145 0.015 0.040 0.008 0.110 0.295 0 0.020 0.770 0.270 0.175 0.021 0.070 0.015 0.130 0.305 10 0.040 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. 2.54 bsc 1.27 bsc 0.100 bsc 0.050 bsc -a- b 18 9 16 f h g d 16 pl s c -t- seating plane k j m l ta 0.25 (0.010) m m sog 16 = -5p (ml145406-5p) case 751g?2 18 9 16 min min max max millimeters inches dim a b c d f g j k m p r 10.15 7.40 2.35 0.35 0.50 0.25 0.10 0 10.05 0.25 10.45 7.60 2.65 0.49 0.90 0.32 0.25 7 10.55 0.75 0.400 0.292 0.093 0.014 0.020 0.010 0.004 0 0.395 0.010 0.411 0.299 0.104 0.019 0.035 0.012 0.009 7 0.415 0.029 1.27 bsc 0.050 bsc -a- -b- p 8 pl g 14 pl -t- d 16 pl k c seating plane m r x 45 0.25 (0.010) b m m 0.25 (0.010) t a b m s s notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. f j lansdale semiconductor reserves the right to make changes without further notice to any products herein to improve reliabil- ity, function or design. lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. ?ypical?parameters whi ch may be provided in lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. all operating parameters, including ?ypicals?must be validated for each customer application by the cus- tomer s technical experts. lansdale semiconductor is a registered trademark of lansdale semiconductor, inc.
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